An embodiment relates generally to patterns of a semiconductor device and a method of forming the same and, more particularly, to patterns of a semiconductor device for forming fine patterns and a method of forming the same.
In the manufacture of semiconductor devices, a number of elements, such as gates and isolation layers, are formed in a semiconductor substrate. To electrically couple the gates together, metal wirings are formed. Junctions (e.g., the sources or the drains of transistors) of the metal wirings and the semiconductor substrate are electrically coupled together by contact plugs.
The gates, the metal wirings, etc. are for the most part formed through a pattern formation process. Thus, an etch target layer (e.g., a gate stack layer, a conductive layer, or an insulating layer) to be patterned is formed over a semiconductor substrate, etch mask patterns are formed over the etch target layer, and the etch target layer is then patterned through an etch process using the etch mask patterns. To form fine patterns through such a pattern formation process it is necessary to form ultra-small and high-performance semiconductor devices.
However, the size of patterns that can be formed is restricted by limitations of equipment used for a pattern formation process, and many difficulties are encountered in overcoming such equipment limitations. Furthermore, in a case in which first patterns and second patterns with different widths are formed on the same plane, mask processes for forming the first patterns and the second patterns must be individually performed. Accordingly, the interval between the first patterns and the second patterns can become irregular or the width of a pattern formed between the first patterns and the second patterns can become irregular due to the overlay margin of a mask for forming the patterns.